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Informationen zum Thema:
Forum:
Hardware
Beiträge im Thema:
2
Erster Beitrag:
vor 2 Jahren, 8 Monaten
Letzter Beitrag:
vor 2 Jahren, 8 Monaten
Beteiligte Autoren:
Dennis Kuschel, Michael Schoettner

Memory-mapped I/O

Startbeitrag von Michael Schoettner am 25.09.2015 07:26

I have learned from Dennis that myCPU devices are accessed using memory-mapped I/O and the /IOEN lines on the backplane decode three I/O areas. Still it is unclear for me how the mapping is done in hardware.

The IRQ-Controller is for example accessed through offset 0x1000, address range 0x2100-0x21FF. So in assembler I can read and write these address locations and access the registers of the IRQ-Controller.

I learned that the lines /IOEN1-3 are driven by IC6 on memory base board.

And address lines A7..A10 go into IC5 on interrupt controller board which switches on the right I/O address. However, this is not fully clear to me. I understand A8 & A9 as selecting the offset range from 0x100 0x1FF but not the semantics of A7 and A10.

Could someone explain that to me?


Many thanks in advance.

Michael
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Antworten:

Hi Michael,

the interrupt controller uses only the address range 0x2100-0x217F. Although the range 0x2100-0x21FF is assigned to the interrupt controller as noted in the list of reserved I/O-addresses, the controller indeed does not use the upper 128 byte. This is why A7 is also connected to the address decoder IC5. A10 is used to avoid enabling the address decoder when the CPU selects an address in the range 0x2400-0x27FF, so only the small address range 0x2100-0x217F gets decoded.

-Dennis

von Dennis Kuschel - am 13.10.2015 05:18
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